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silicom PE2G2BPI35A bypass card
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| Model No.︰ | PE2G2BPI35A |
| Brand Name︰ | silicom |
| Country of Origin︰ | Israel |
| Unit Price︰ | CNY ¥ 1850 / pc |
| Minimum Order︰ | 1 pc |
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Bypass /Disconnect:
Bypass Ethernet ports on Power Fail, System Hangs or Software Application Hangs
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Disconnect ports on Power Fail, System Hangs or Software Application Hangs
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Software programmable Bypass or Normal or Disconnect Mode
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On Board Watch Dog Timer (WDT) Controller
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Software programmable time out interval
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Software Programmable WDT Enable / Disable counter
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Software programmable Bypass Capability Enable / Disable
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Software programmable Disconnect Capability Enable / Disable
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Programmable state (Bypass mode or Normal mode or Disconnect mode) at Power up
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Programmable state ( Bypass or Normal mode) at Power off
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Emulates standard NIC
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Performance Features:
16 Transmit and Receive queues per port
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Up to 16 queues of Receive Side Scaling (RSS) minimize CPU utilization across multiple processor systems
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Support for 8 pools of virtual machine Device Queues ( VMDq) per port
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Support Direct Cache Access ( DCA)
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Support Intel I/O AT 2.0
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TSO interleaving for reduced latency
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UDP TSO
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Minimized device I/O interrupts using MSI and MSI-X
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Offload of TCP / IP / UDP checksum calculation and TCP segmentation
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SCTP receive and transmit checksum offload
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Packet interrupt coalescing timers (packet timers) and absolute- delay interrupt timers for both transmit and receive operation
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Copper Gigabit Ethernet 1000Base-T:
Independently copper Gigabit Ethernet channels support six, four, two and one Gigabit Ethernet (1000Base-T), Fast Ethernet (100Base-Tx) and Ethernet (10Base-T)
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Triple speed 1000Mbps (1000Base-T), 100 Mbps (100Base-Tx) and 10 Mbps (100Base-T) operation
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Nway auto negotiation automatic sensing and switching between 1Gbps full duplex and 100 / 10 Mbps operations Simplex or Full Duplex
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RJ-45 female connectors
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Common Key features:
Host Interface PCI-Express 4X Lane (Version 1.1).
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High performance, reliability, and low power use in Intel 82576 dual integrated MAC + PHY and SERDES chip controller
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Ultra deep packet buffer per channel lowers CPU utilization
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Hardware acceleration that can offload tasks from the host processor. The controllers can offload TCP/UDP/IP checksum calculations and TCP segmentation
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Priority queuing – 802.1p layer 2 priority encoding
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Virtual LANs –802.1q VLAN tagging
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Jumbo Frame (9.5KB)
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802.x flow control
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PCI-SIG SR IOV (8 VF)
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Multicast/ broadcast Packet replication
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Statistics for SNMP
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Supports Vital Product Data (VPD)
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Integrated LinkSec security engines
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Supports IEEE 1588
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LEDs indicators for link/Activity/Bypass/ Disconnect Mode status
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Product Image
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